The field of the invention is the packaging of electronic devices such as semiconductors, and particularly, the cooling of such devices.
Modern digital and analog integrated circuits (“chips”) are consuming ever-larger amounts of DC power as the number of transistors per unit area is increased in digital chips, and as the amount of output power required of analog chips (such as power amplifiers) is increased through the use of improved design techniques, more capable transistors, and new transistor materials (in the latter case: silicon germanium bipolar transistors; indium phosphide, gallium nitride, and silicon carbide transistors). The chips convert all or much of the DC power that they absorb from the power supply into heat: in the case of digital circuits, almost all of the DC input power becomes waste heat: and in the case of analog (i.e., amplifier) chips, 50-80% of the DC input power becomes waste heat. This waste heat must be removed to assure that the chip (or multiple chips in a subsystem) do not self-destruct. Silicon and indium phosphide chips can operate at temperatures up to approximately 85° C. Gallium nitride and silicon carbide chips can survive to much higher temperatures but still have a maximum operating temperature. The problem is that with ever-tighter packing of transistors on all of these chips, the power densities (heat loads) of these chips, measured in watts of power per square centimeter of chip area, are increasing very dramatically. Several years ago, a chip with thermal densities above 10 W/cm2 was the norm; presently, even silicon chips have been designed with power densities of 350 W/cm2. Prototype versions of gallium nitride and silicon carbide chips have been demonstrated “in the laboratory” operating at power densities in the range of 1500-3500 W/cm2 and III-V compound semiconductor chips operate in the range of 450 W/cm2. If these heat loads are not removed and the chips held to below their maximum operating temperatures, they will not only cease to function but may even completely self-destruct.
Many mechanisms have been used to cool “hot” chips. The two most common are conduction cooling and convection cooling, and the two are often combined. In the former, a chip is bonded (soldered or epoxy-attached) into a package which contains a large metal mass, such that the heat flows from the back of the chip directly into the metal mass, and then into a finned radiator, over which cool air is blown to remove the heat. In some cases, the lower temperature “sink” is a cold plate through which cold water, fluorocarbon, or other working fluid is passed as a transport fluid. In fact, for each level of chip power density, there are a range of cooling options that best match the overall system design considerations. The chart in FIG. 1 illustrates this point. As the overall power density of the chip increases, the cooling options decrease, and at power densities above 100-200 W/cm2, the options become quite limited. Chip cooling by directly pumping a working fluid such as fluorocarbon onto the chip(s) has been developed and cutting microchannels in the back of the chips and pumping liquid through the microchannels has been developed in an effort to operate at these power densities.